The present invention relates to a semiconductor memory device and a method for fabricating the semiconductor memory device and, in particular, to a memory cell structure of a semiconductor memory device that uses a high-xcexa film or a ferroelectric film.
Recently, embedded-DRAM processes for combining DRAMs with high-performance logic circuits have been put into practical use in multimedia applications requiring large memory capacity and high data transmission speed.
However, since the conventional DRAM process requires high-temperature heating process for formation of a capacitive insulating film of a capacitor functioning as a memory capacitor, it has deficiencies such as worsening an impurity concentration profile of doped layers of a transistor in a high-performance logic circuit. In addition, it is also desirable to avoid the high-temperature heating process as far as possible in a memory single unit process for a DRAM, an FeRAM or the like in realizing miniaturization of a memory cell transistor.
Therefore, it has become indispensable to develop an MIM (metal-insulator-metal) capacitor in which a high-xcexa film that can be formed at a low temperature and is capable of making a memory size fine is used as the capacity dielectric film of a memory capacitor. As this high-xcexa film, there is a dielectric film having the perovskite structure such as a BST film ((BaSr)TiO3 film). On the other hand, Pt that has high oxidation resistance is generally considered prospective as a material for forming a metal electrode of this MIM capacitor. In addition, dielectric films having the perovskite structure such as an SBT film (SrBi2Ta2O9 film) and a BTO film (Bi4Ti3O12 film) are often used as a ferroelectric film.
However, the conventional MIM capacitor functioning as a memory capacitor has the following problems.
First, when a contact hole is formed directly on a Pt electrode (upper electrode) provided on a capacitive insulating film, a reducing atmosphere or the like at the time when a contact plug is formed is likely to affect properties of the capacitor adversely. This is because oxygen deficiency occurs in a dielectric film due to the reducing atmosphere as, in general, a dielectric film is often an oxide. In particular, when the capacitive insulating film is a high-xcexa film or a ferroelectric film, the possibility of the occurrence of oxygen deficiency is high. Deterioration in the properties by oxygen deficiency occurs remarkably in a dielectric film having the perovskite structure.
In addition, in a device such as a DRAM in which a Pt electrode is not used, since it is difficult to share existing equipment in a step such as the formation of a contact in a Pt electrode, which is a new material, operation in dedicated equipment becomes necessary. For example, in such a time when a contact hole that reaches a Pt electrode is formed in an interlayer insulating film, since Pt is sputtered when the Pt electrode is exposed, Pt deposits on the wall surface of a chamber, members in the chamber, etc. If this chamber continues to be used, Pt enters an active region or the like of a transistor to affect transistor operations adversely.
The present invention has been devised in view of the above drawbacks, and it is an object of the present invention to provide a semiconductor memory device having good properties of an MIM capacitor and a method for fabricating the semiconductor memory device by taking measures for inhibiting deterioration of a dielectric film and, at the same time, preventing an electrode material from mixing in a transistor region.
In addition, it is another object of the present invention to provide a semiconductor memory device and a method for fabricating the semiconductor memory device that can reduce manufacturing costs by making dedicated equipment unnecessary.
A semiconductor memory device of the present invention comprises: a memory capacitor that is provided on an insulating layer on a semiconductor substrate and constituted by a lower electrode, an upper electrode and a capacitive insulating film interposed between the lower electrode and the upper electrode; an extension of the upper electrode from the upper electrode of the memory capacitor; a dummy conductor member that is provided such that at least a part of the dummy conductor member comes into contact with an underside of the extension of upper electrode; and upper layer interconnect that is electrically connected to the dummy conductor member.
Consequently, since the upper electrode is connected to the upper layer interconnect via the extension of upper electrode, a dummy lower electrode and the dummy conductor member, it is not unnecessary any more to form a contact hole above the upper electrode and a step in which the upper electrode is exposed to a reducing atmosphere becomes unnecessary. As a result, it becomes unlikely to cause oxygen deficiency in, for example, a capacitive insulating film consisting of BST and deterioration in the properties of the capacitive insulating film can be prevented. In addition, for example, if an electrode is formed of Pt, formation of the lower electrode, the dummy conductor member and the upper electrode is performed by dedicated equipment for Pt film formation. Thus, it becomes unlikely that equipment for the formation of logic circuit elements is contaminated.
The dummy conductor member may consist of a conductor film filling a trench provided in the insulating layer.
The dummy conductor member may further include local interconnect provided on the semiconductor substrate under the insulating layer and a plug that pierces through the insulating layer to electrically connect the extension of upper electrode and the local interconnect.
Since the local interconnect is further provided with a bit line formed below the memory capacitor across the insulating layer and is formed of a conductor film, which is the same as the bit line, a structure suitable for a memory with a capacitor over bit line utilizing the conductor film for the bit line is obtained.
Since at least a part of the extension of upper electrode overlaps the conductor plug when it is viewed two-dimensionally, the upper electrode and the upper layer interconnect are securely connected.
The semiconductor memory device further comprises: an isolating insulating film that is provided on the semiconductor substrate below the insulating layer; a memory cell transistor formed in a region of the semiconductor substrate, the memory cell transistor including a gate electrode and doped layers defined within the semiconductor substrate below the gate electrode to horizontally sandwich the gate electrode there between; local interconnect that is provided on the isolating insulating film and is formed of the same conductor film as the gate electrode; and a conductor plug that pierces through the insulating layer and is connected to the local interconnect. Therefore, a structure that can be applied to both a memory with a capacitor over bit line and a memory with a capacitor under bit line is obtained utilizing a conductor film (a polysilicon film, etc.) for the gate electrode.
The semiconductor memory device further comprises: a memory cell transistor that is provided on the semiconductor substrate and has a gate electrode and doped layers defined within the semiconductor substrate below the gate electrode to horizontally sandwich the gate electrode there between; local interconnect that is formed of another doped layer, which is provided separately from the doped layers on the semiconductor substrate; and a conductor plug that pierces through the insulating layer and is connected to the local interconnect. Therefore, a structure that can be applied to both a memory with a capacitor over bit line and a memory with a capacitor under bit line is obtained utilizing a step for forming source and drain regions.
Since the upper layer interconnect is in contact with the dummy lower electrode, a structure that can be applied to a memory with a capacitor over bit line and a memory with a capacitor under bit line is obtained with a relatively simple structure.
Since the memory capacitor has a clyndrical lower electrode, a capacitive insulating film and an upper electrode, a semiconductor memory device in which memory cells are arranged at a relatively high density is obtained.
The capacitive insulating film is preferably a high-xcexa film or a ferroelectric film.
A first method for fabricating a semiconductor memory device of the present invention is a method for fabricating a semiconductor memory device that comprises a memory capacitor that is constituted by a lower electrode, an upper electrode and a capacitive insulating film interposed between the lower electrode and the upper electrode, and upper layer interconnect that is electrically connected to the upper electrode of the memory capacitor, comprising: a step (a) of forming local interconnect on a semiconductor substrate; a step (b) of forming a first conductor film on the semiconductor substrate after the step (a); a step (c) of patterning the first conductor film to form at least the lower electrode; a step (d) of forming a dielectric film functioning as the capacitive insulating film covering the lower electrode; a step (e) of forming a second conductor film on the semiconductor substrate after the step (d); a step (f) of patterning the second conductor film to integrally form the upper electrode covering the entirety of the lower electrode and an extension of upper electrode that covers at least a part of the local interconnect and continues to the upper electrode; and a step (g) of forming the upper layer interconnect, which is electrically connected to the upper electrode, on the semiconductor substrate via at least the local interconnect and the extension of upper electrode after the step (f).
With this method, since it becomes possible to connect the upper electrode to the upper layer interconnect via the local interconnect and the extension of upper electrode, it is not necessary any more to provide a contact hole on the upper electrode in the manufacturing process as conventionally did, whereby the capacitive insulating film can be prevented from being reduced.
The method for fabricating the semiconductor memory device further comprises; a step (a2) of forming a first insulating film on the semiconductor substrate containing the local interconnect; and a step (a3) of forming a first conductor plug and a second conductor plug that pierce through the first insulating film and electrically connect to the local interconnect together, after the step (a) and before the step (b), wherein, in the step (f), the extension of upper electrode is formed to cover at least a part of the first conductor plug and, in the step (g), after forming a second insulating film on the semiconductor substrate, a trench for embedding interconnect that reaches the second conductor plug is formed in the second insulating film, and a conductive film is embedded in the trench to form the upper layer interconnect, whereby the semiconductor memory device of the present invention can be realized.
In the step (a), the local interconnect consists of the same conductor film as a bit line and is formed simultaneously with forming the bit line, whereby the semiconductor memory device of the present invention can be manufactured with fewer steps.
In the step (a), the local interconnect consists of the same conductor film as a gate electrode of a memory transistor and is formed simultaneously with forming the gate electrode, whereby the semiconductor memory device of the present invention can be manufactured in fewer steps.
In the step (a), the local interconnect consists of the same doped layers as source and drain regions of a memory transistor and may be formed simultaneously with forming the source and drain regions and separately from the source and drain regions.
In the step (a), even in the case in which the local interconnect is formed in a first insulating film formed on the semiconductor substrate simultaneously with forming a memory cell plug to be electrically connected to a source region of a memory cell transistor, the steps of manufacturing the semiconductor memory device of the present invention can be reduced.
The step (c) includes a step of forming a dummy lower electrode consisting of the first conductive film that separates from the lower electrode and covers at least a part of the local interconnect, and the local interconnect and the extension of upper electrode are electrically connected via the dummy lower electrode, whereby the semiconductor memory device of the present invention can be manufactured easily even in the case in which the dummy lower electrode is provided.
In the step (d), the dielectric film covering the lower electrode and the dummy lower electrode is formed, in the step (e), the second conductor film covering the dielectric film is formed, and after the step (f) and before the step (g), a step of pattering the dielectric film using the same etching mask as in forming the upper electrode and the extension of upper electrode to form a dielectric film for a capacitive insulating film, a step of etching at least a part positioned between the dummy lower electrode and the extension of upper electrode in the dielectric film for a capacitive insulating film to form the capacitive insulating film simultaneously with forming an inter-electrode space, and a step of causing the extension of upper electrode on the inter-electrode space to deform by heating process to cause the extension of upper electrode and the dummy lower electrode to come into contact with each other are further included, whereby an upper electrode and upper layer interconnect are electrically connected by the heating process between the step (f) and the step (g). Thus, the upper electrode is never exposed to the reducing atmosphere during the manufacturing process and deterioration of the capacitive insulating film can also be prevented.
After the step (a) and before the step (b), a step (a4) of forming a first insulating film on the semiconductor substrate containing the local interconnect and a step (a5) of forming a first conductor plug and a second conductor plug for piercing through the first insulating film to electrically connecting to the local interconnect together are further included, and after the step (a5), a step (a6) of forming an insulating film for step on the semiconductor substrate and a step (a7) of forming a first opening for forming the lower electrode of the memory capacitor and a second opening for forming a dummy lower electrode to be connected to the first conductor plug in the insulating film for step are further included. In the step (c), the lower electrode is formed on the side and the bottom of the first opening and the dummy lower electrode is formed on the side and the bottom of the second opening, in the step (f), the extension of upper electrode is formed so as to cover at least a part of the dummy lower electrode, and in the step (g), after forming a second insulating film on the semiconductor substrate, a trench for embedding interconnect that reaches the second conductor plug is formed in the second insulating film and the insulating film for step and a conductive film is embedded in the trench to form the upper layer interconnect, whereby, for example, upper layer interconnect and an upper electrode provided by a damascene method can be electrically connected.
The dielectric film is preferably a high-xcexa film or a ferroelectric film in realizing the semiconductor memory device.